bist , boundary scan , Jtag, Soc, Tcl, Python, Shell Scripting, Silicon Validation, Dft, Design for Test, Scan Insertion, Scan Compression, ATPG, MBIST, LBIST, IJTAG, IEEE 1149.1, IEEE 1500, IEEE 1687, TestMAX, DFT Compiler, TetraMax, Tessent, Cadence Modus, occ, EDT, RTL, ASIC, Semiconductor, Vlsi

Jtag, Perl, Verilog, Python, Tcl, Sta, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT Compiler, Scan Insertion, Physical Design, Cadence Modus, RTL synthesis, ATPG, Scan Compression, DFT Architecture

Understanding of low-power design flows, ATPG and test coverage analysis using industry standard tools, Gate level simulation using Synopsys VCS and Verdi, Knowledge of fault models, JTAG Scan Compression and ASST implementation, Fluent in RTL coding for DFx logic, Exposure to post-silicon testing and tester pattern debug, Familiarity with SystemVerilog and UVM, Understanding of DFT Architectures and micro-architectures, MBIST planning implementation and verification