ARM based SoC verification, Industry standard protocols, Power aware simulations, ASIC verification concepts, Gate level simulations

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi

C, Spi, I2c, Firmware, Peripherals, Usb, Can, Gpio, Pcie, Ethernet, PLLs, Specialized hardware accelerators, Interrupt Controllers, GPUs, J-TAG, Embedded Platforms, SoC hardware blocks, DSPs, ICE debuggers, Kernel and user-space components, Heterogeneous compute platforms, UFS, GIC, ARM CPUs, Real-time SW development, Low-level drivers, Clocks

lattice , C, Pcie, Verilog, System Verilog, Usb, Ethernet, Ddr3, ARM Cortex platforms, Microsemi, Veloce platforms, UVM-acceleration, processor architectures, RTL synthesis concepts, FPGA architectures, embedded processors, VirtuaLAB environments, SERDES, SystemC-DPI testing methodologies, AMBA, APB, DSP theory, Xilinx, AHB, Altera

Kubernetes, Zephyr, Mqtt, C, Freertos, Ansible, Rtos, Ble, Https, Nosql, Bash, Python, Docker, Terraform, Coap, Wi-Fi, Lambda Functions, Cellular, MPU architectures, MCU, Bare-metal environments, Cloud Native services, Event-driven architecture

JIRA, C, Linux, Gitlab, Qnx, Android, Python, Confluence, Android BSP drivers, audio IPs, ISO26262, automotive technologies, display and graphics IPs, Autosar, Embedded Android system software development

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP