Regression Analysis, System Verilog, scripting languages like Perl Python, bus protocols like AHB AXI, Uvm, Modem Wireless IP verification, clock domain crossing designs, low power verification methodology, bug-triage, verification environment and testbench components, Power Aware Verification, formal verification, Code Functional coverage, post-Si debug, RTL verification in C System Verilog UVM, Cadence and Synopsys simulator tools, PA GLS verification of DC and PD PG Netlist, digital front end ASIC design verification, Assertion for temporal logic testing