System Verilog, Design Verification, Functional Verification, Environment Development, Uvm, Test Plan Generation

Ovm, Functional Verification, VLSI Verification, Specman e, Uvm, eRM, Assertions, formal verification, Constrained Random Verification

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog