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Sr Principal Design Engineer

Cadence
C
Bengaluru

Skills:

Verilog, Pcie, Debugging, Rtl Design, systemverilog, Uvm, CXL, PXC, Vlsi, Digital Design, SoC Verification

Early Applicant

Sr Principal Design Engineer

Cadence Design Systems (India) Pvt Ltd
C
Bengaluru

Skills:

System Verilog, Pcie, Uvm, PXC, CXL, RTL Design using Verilog

Early Applicant

Staff/ Sr Staff/ Principal Engineer, Digital Design

Renesas Electronics
Bengaluru, India

Skills:

static timing analysis, VHDL, clocking resets, Timing Analysis, verification methodologies, EDA tools for synthesis, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC, RTL design using Verilog, low-power design techniques, Simulation

Early Applicant
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