Debugging, Test Planning, Simulation, systemverilog, Uvm, IP verification, Testbench development, Verification architecture, Mentoring

Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology

CPF UPF formats, Digital timing concepts, DFT concepts, Digital circuit design, power analysis, Functional simulation tools, coverage analysis, AMBA protocols, Synthesis tools, Timing Closure, spyglass, Design For Testability, RTL Coding, Lint and CDC analysis, SoC clock architecture, ARM based SoC architecture

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

C, Digital Signal Processing, Scripting Languages, System Verilog, Python, CPU architecture, ASIC design methodology, Block level verification using SV UVM, VHDL, Basic circuit design, CMOS technology, device physics, SOC systems