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Lead SOC verification Engineer:

AMD is seeking a highly experienced SMTS Design Verification Engineer to lead verification efforts for next-generation Server SoC designs. The ideal candidate will possess deep expertise in developing scalable testbenches using SystemVerilog and UVM, demonstrate strong proficiency in formal and assertion-based verification methodologies, and have a solid understanding of RTL integration.

Key Responsibilities:

Lead the development and execution of scalable, reusable SystemVerilog/UVM testbenches for server-class SoC verification.
Drive verification strategy and planning for complex server SoC architectures, including integration of high-speed interfaces and subsystems.
Develop and deploy SystemVerilog Assertions (SVA) for assertion-based verification, ensuring protocol and interface correctness across SoC boundaries.
Apply formal verification techniques, including property checking and formal exploration, to critical SoC blocks.
Oversee RTL integration activities, ensuring seamless connectivity, clocking, and power domain crossings within the SoC.
Collaborate with cross-functional teams (RTL, DFT, validation, firmware, and physical design) to resolve complex design and verification challenges in server SoC environments.
Lead coverage analysis and closure, including functional, code, and formal coverage metrics for SoC domains.
Mentor and guide junior engineers in best practices for scalable testbench architecture, assertion development, formal verification, and RTL integration.
Document verification strategies, methodologies, and results to drive continuous improvement and knowledge sharing across AMD's server SoC teams.

Required Skills and Experience:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
10-15 years of experience in design verification, with a focus on scalable SystemVerilog/UVM testbench development for complex SoCs.
Proven experience in developing and deploying SystemVerilog Assertions (SVA) for assertion-based verification.
Strong hands-on experience with formal verification tools and methodologies (e.g., property checking, connectivity checks, formal signoff).
Advanced scripting skills (Python, Perl, etc.) for automation and testbench infrastructure.
Excellent problem-solving, debugging, and communication skills.
Demonstrated leadership in driving verification methodology and mentoring teams.
Solid know-how in RTL integration, including clocking, reset, power domains, and static checking (CDC/RDC).

Preferred Qualifications:

Experience with silicon bring-up and lab validation of server SoCs.
Familiarity with DFT, synthesis, and timing closure for high-speed interfaces in server environments.
Prior work in large-scale SoC environments and cross-site collaboration.

Experience with AI/ML-based verification tools and emulation/FPGA validation flows

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available

This posting is for an existing vacancy.