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Job Description:

Principal Engineer - Implementation

Company Description

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products.

Job Description

Microchip AES Design team in Bangalore is looking for an experienced and motivated Backend Implementation Engineer to perform Synthesis & STA for larger SOCs. As a member of Implementation team, you will be responsible for timing constraints (SDC) generation, timing closure and Low Power checks for multiple blocks and top level. The candidate should have strong experience with STA tools like Tempus/Primetime. The candidate should have in depth knowledge of timing constraints.

Location: Bangalore, India

Requirements/Qualifications:

Job Responsibilities:

The Employee Is Responsible For Implementation Activities Of Multiple Large & Complex Blocks & Sub-system Implementation From 16nm To 3nm And Below Technology Nodes. The Employee Is Expected To Take Ownership Of Full Chip/Subsystem Complex Design & Flow Challenges, Which Would Include:

Perform Synthesis and STA timing closure for multi-million hierarchical complex designs.
Lead and drive team members to complete Implementation activities.
Complete timing closure for blocks & top level in advanced nodes.
Develop constraints/SDC and perform pre & post-layout timing closure.
Perform CLP and LEC for both full chip and block level.
Experience on UPF/CPF would be an added advantage.
Optimize design performance through timing closure and power optimization.
Develop and maintain design constraints and timing models.
Analyze and debug timing issues.
Inserting DFT logic for both block and top level.
Analyze Physical timing challenges and provide guidance for placement & CTS.
Occasional travel needed.
Use metric-driven techniques to help ensure first-pass working silicon.
Communicate regularly with the implementation and project team to resolve issues, and communicate status to Project Management.

Job Qualifications:

This position requires at least B.E/B.Tech/M.Tech in Electronics with 9+ years of Synthesis & STA experience in a fast-paced environment with following experience.

Expertise in Implementation activities: Synthesis, STA, LEC, Low Power Checks.
Static Timing/Crosstalk Analysis and timing closure
Must have understanding of DFT insertion.
Expertise with Synthesis & STA Tools (Genus, Fusion Compiler, Primetime or Tempus).
Experience on Conformal LEC and CLP will be added advantage.
Strong programming knowledge in Perl, TCL, and/or Shell and Python Scripting
Excellent oral and written communications skills to work with teams across the globe
Strong understanding of timing closure and power optimization techniques
Must have good understanding of Verilog

Travel Time:

0% - 25%

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