C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, Processor Micro-Architecture concepts, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools, IP Sub-System SOC level ASIC verification

Vcs, Makefile, Shell, System Verilog, Python, Perl, Questa, formal verification, UVM methodology, Assertion-based verification, Xcelium, Vivado Simulator, Constrained-random verification

Vcs, Makefile, Shell, Perl, Python, High-speed interface protocols, Assertion-based verification, Xcelium, Functional and code coverage closure, Formal verification tools and methodologies, PSL, Uvm, systemverilog, CI CD verification pipelines, Constrained-random verification, Questa, Debugging RTL, Regression infrastructure, AI-assisted verification tools, Vivado Simulator, SVA, Verification automation frameworks

Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, verification management tools, Uvm, SVA