Logic Design, Static-timing closure, Verification, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Timing signoff, Gate-level simulations, Block-level function verification, RTL coding techniques, formal verification

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

Vcs, Static Timing Analysis, Verdi, ATPG tools, DFT ATPG, TetraMax, FSDB, Debug skills, Scripting skills, Timing Closure, Scan Patterns, Siemens, Mentor Graphics, Synopsys, ATPG scripts

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking