Bluetooth, Zephyr, Spi, MATLAB, Jtag, Freertos, I2c, Uart, Gpio, C Programming, Ble, Timers, Embedded Software Firmware Development, Low-level device drivers, Threadx, Clock management, LoRa, DMA, Low-power embedded design, Sleep wake mechanisms, SWD, Protocol analyzers, Object-oriented concepts, Wi-Fi, UWB MAC, Embedded debugging tools, RTOS environments, Logic analyzers, ARM Cortex-M, Power sequencing, UCI

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator

boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis

bist , Jtag, ATPG, Cadence Modus, Synopsys DFTMAX, Scan Insertion, DFT methodologies, Fault Simulation, Mentor Tessent

boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax