synopsys primetime , Perl, Python, Tcl, OCV, Case Analysis, setup hold analysis, multicycle paths, Cadence Tempus, SDC timing exceptions, path-based analysis, timing constraints development, POCV, Timing Closure, ECO methodologies, AOCV

synopsys primetime , Synopsys FusionCompiler, AI ML Integration, Advanced Node Experience, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, Advanced Clocking

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis

Place and Route (P&R, Tcl Scripting, Sta, Timing constraints quality assessment, SynopsysPT-SI, Signoff power analysis and optimization, Analysis, problem-solving skills, multi-voltage designs, Methodology, Cadence Tempus, timing variation aspects, Timing Analysis, EDA tool benchmarks, timing ECO flows, Debug, Block-level and chip-level signoff STA