Perl, Python, Logic Design, DFT Engineering, Uvm, Architecture Verification, Testplan Development, IOBIST Test-logic, Industry-standard Verification Flows, Constrained Random Testing, Automation Flow Development, Profiling Tools, Pre-Silicon Simulation and Debug, Coverage Metrics

Boundary Scan JTAG, MBIST, pattern generation validation, DFT architecture, scan implementation, Memory IP Test Simulations, IJTAG, retargeting activities, DFT implementation, EDT, OCC integration, boundary scan methodologies, debug and analysis

DFT strategies, Tessent, EDA Tools, ATPG pattern generation, MBIST, Cadence, Synopsys, IJTAG, Scan compression

Memory BIST, TetraMax, DRC Coverage, SSN, occ, Dft, ICL, Scan Insertion, ATPG, pdl, Debug, Simulation, Sms, Synopsys, IJTAG

Scan, HDLs, MBIST, DFT architecture definition, Tempus, ATPG flow implementation, scripting skills in Perl, Genus, tessent DFT, JTAG boundary scan, Cadence digital implementation tools

Clp, Perl, Python, Tcl, Scan Insertion, Hybrid-TK Compression, SoC DFT Architecture, ATPG DRC analysis, P1500 implementation, Memory BIST implementation, JTAG BSCAN, MBIST, LEC, Bridging Cell-aware iddq fault models, iJTAG, Stuck at TDF, Logic and DRC analysis, Test coverage debug, ZERO delay and SDF based scan, LPCT, JTAG simulations, power analysis methodologies, LBIST

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, timing fixes corrective actions for timing violations, ASIC DFT

SoC-level DFT Integration, JTAG IEEE 1149.1, DFT DRC and Debug, MBIST Implementation and Verification, ATPG and Fault Coverage Analysis, Scan Insertion and Scan Compression