Perl, Python, RTL development environments, test bench infrastructure, low power verification, verification methodologies, system level performance analysis, emulation platforms, Uvm, automation scripts, systemverilog

memory controllers , Verilog, Python, Perl, DDR5, Electrical, fabric and interconnect architectures, Computer Science, high-bandwidth memory subsystems, systemverilog, front-end design, Design Verification, hardware accelerators, SimXL, JEDEC compliance, power-aware verification methodologies, formal verification, LPDDR5, cache coherency protocols, SoC-level verification, HBM, physical layer PHY training, pre-silicon emulation platforms

Spi, Uart, Usb, Verilog, I2c, Python, Perl, Can, safety simulators, GLS, vManager, Uvm, Specman, systemverilog, Xcelium, Cadence Tools, AI ML-based DV, VHDL, post-silicon verification, AHB, Formal JG applications, PAGLS