Debugging, Python, systemverilog, UVM Methodology, Testbench Development, Simulation, Low-Power Verification, Functional Safety Simulation, HDL Design

Tcl, Bash, Python, Perl, Sound Forge, Microsoft Word, multimedia authoring tools, testbench creation, Simulation, UVM methodology, systemverilog, Adobe Acrobat, Microsoft Powerpoint, camtasia, HDL design, Verification, Debug