Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

power supplies , C, I2c, Python, Labview, Automation of Equipment and Tests, SVI3, scopes, Relays, ATE programs, PMBUS, Computer to IC board communications, Basic circuits on bread board, SVID, Probes, SPMI, Power Chip Communication protocols, Validation related equipment, Load Slammer, FPGAs, Multi-meters, Bench Validation, Debug of Power Management ICs, Design PCBs, Analog switches

react.js , Golang, Sql, Python, GenAI models, Google BigQuery

System Verilog, Asic verification, SoC Verification, digital design verification, Uvm, GIT version control

rtl verification , simvision , Gen5., Pcie, PCI Express, Design Verification, design verification testing, DV, systemverilog, Uvm, SVA, TLP, DLLP, LTSSM, Verification IP, vip, Functional Coverage, Assertions, Axi, Vlsi, Semiconductor, Verdi, DVE, Gen3, Gen4

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

Usb, Fpga, Soc Architecture, Pcie, Perl, Debugging, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, AMBA, formal verification, Test Bench, transaction level modeling, AXI4

Numpy, Git, Pandas, Pytorch, Version Control Systems, Python, machine learning frameworks, OpenAI’s GPT models, Hugging Face, data processing libraries, prompt engineering