analog layout design fundamentals, Extraction, techfile constraints, advance node, skill scripts, Cadence layout tools, Physical Verification, foundry process methodology, analog layouts, EMIR analysis, virtuoso, layout automation tasks, IC design technology

virtuoso, Analog back-end flow, Advance Node layout and design rules, Physical Verification, Foundry process methodology, Analog layout design fundamentals, Cadence layout tools, IC design technology, Extraction, EMIR analysis